Improved PWB test methodologies

Printed Wiring Board (PWB) and Printed Circuit Board Assembly (PCBA) testing aims to ensure an error free board after the etching and the assembly processes. After the etching process, several types of errors might occur such as opens and bridges, which are already, showstoppers in Direct Current (DC) applications. Mouse bites, spurs and others such as weak traces, which can be problematic in Radio Frequency (RF) and high-speed signals applications. Loading expensive component on defective boards can be economically catastrophic especially for high volume production. The rule of ten which has been reported by the production experts says that the defect costs ten times when detected in the next testing phase. Bare board also needs to be tested for the characteristic impedance correctness due to the process variations and the compounding raw material tolerances that can cause characteristic impedance mismatches. Although testing the characteristic impedance is not in interest in some application, sampling the characteristic impedance for a specific design is one way to test the manufacturing process stability for better tuning, otherwise PWBs might differ from each other even within the same batch. In addition to the possibility of defective PWB, the assembly process is never perfect to achieve 100 % of PCBA yield due to the possible errors in the process steps such as paste application, pick and place operations and soldering process which might lead to bridges, opens, wrong or miss oriented components.For low volume production, flying probes test technology is cost efficient as compared to bed-of-nails. The performance of the flying probes system depends on the test algorithm, the mechanical speed and the number of probes. To reduce the initial and maintenance costs of the probing technology and to accelerate the test time, Paper A introduces a new indirect method to test PWB continuity and isolation testing using a single probe for testing both continuity and isolation at the same time. RF signal is injected into the trace under test, instead of a DC current. The phase shift between the incident and the reflected signals is measured as it carries the information about the correctness of the trace when compared with a reference value of the same trace in the correct board. The method shown an important capability for detecting PWB defects such as as opens, DC and RF bridges, exceeded and different width lines. The margin in the measurement between a defective and a correct board, which depends on the type of the defect, is about 7 % to 68 %. Applying this approach to PCBA testing led to significant margins between correct and defective interconnect. The test cases in paper C shown 40 % and 33 %. Moreover, this margin has been proven to be important even for short microstrip line, which intended to connect two typical IC pins. This technique is strongly recommended to be applied to PCBA testing where probing is feasible. The approach can be applied to the complete layout testing or to boost a test strategy whose test solutions are not covering 100 % of the possible defects.By applying this test solution to bed-of-nails equipment, 50 % of the probes will be reduced, on the other hand, for a given design with NI isolated traces and NA adjacent pairs, employing this solution to flying probes system with two probes, leads to the reduction of the number of tests from (NI+NA) tests to NI tests as isolation and continuity are performed in one go. Flying probes system involves mechanical movements, which dominate the test time, reducing the number of the mechanical movements increases dramatically the test throughput. On the other hand, this method is believed to be extremely fast to test the correctness of the characteristic impedance which is prone to variations due to the instability of the PWB manufacturing process, in the same time one could employ the method to evaluate the process stability by checking after each batch of PWBs. Paper B and D provide insight into the impact of the PWB manufacturing variations on the characteristic impedance. Moreover single probe approach is believed to have a good potential for Sequential Build-Up (SBU) interconnects testing where connections between component pads and the upper layers are often impossible to test with the current test technologies.Godkänd; 2012; 20121123 (abdren); LICENTIATSEMINARIUM Ämne: Industriell elektronik/Industrial Electronics Examinator: Professor Jerker Delsing, Institutionen för system- och rymdteknik, Luleå tekniska universitet Diskutant: Associate Professor Erik Larsson, Linköpings universitet Tid: Tisdag den 18 december 2012 kl 13.00 Plats: A1514, Luleå tekniska universitet</p

Contactless Test of Circuit Boards

Electronics are still continuing to respond to the small-feature size requirement for economical, performance and environmental benefits.Due to the non-idealities in the manufacturing process of circuit boards, electronics production yield is never 100 %. To maintain a good reputation of a product brand, testing of circuit boards is highly recommended before shipping to the customer.Because of the strive for high density electronics, an increasing percentage of circuit boards will not be accessible for the current test approaches. New technologies as High-Density Interconnect (HDI), Through-Silicon Via (TSV), embedded chips and Sequential Build-Up (SBU) circuit boards will even further increase the challenge for the test business. Current test approaches to dense circuit boards most often require extra test pads and thus additional cost and size. Already the use of today's standard Ball Grid Array (BGA) packages has introduced difficulties to conventional Printed Circuit Boards (PCBs) testing. To deal with these challenges on testing and to enhance the current test methodologies, this thesis addresses improvements to the existing test methodologies and also proposes test approaches usable in conjunction with Sequential Build-Up (SBU) production of circuit boards.Firstly, this thesis introduces a new indirect method to test Printed Wiring Board (PWB)/PCB where probing is feasible. A Radio Frequency (RF) signal is injected into the trace under test, instead of a DC current. The phase shift between the incident and the reflected signals is measured as it carries information about the Unit Under Test (UUT). The solution implies faster and lower probing technology resources as it is possible to test against opens and shorts in one pass, it uses a single probe. Based on several cases, manufacturing defects are discriminated with significant margins.Secondly, a contactless approach for testing PCB is proposed for interconnects where probing is not feasible. A test trace is employed on another test board as a sensor, which reads the terminations of the trace of the UUT. The results have shown the feasibility of this concept to be applied to the state of the art HDI and to conventional PCBs with hidden interconnects. Design for Testability (DfT) rules have been created for robust error detection that allow fault detection in the range of a few Parts per Billion (PPB) while accounting for component specification variabilities of 10 - 20 %. It has been shown that the maximum test frequency is around 6 GHz, which is manageable.Godkänd; 2014; 20141007 (abdren); Nedanstående person kommer att disputera för avläggande av teknologie doktorsexamen. Namn: Abdelghani Renbi Ämne: Industriell elektronik/Industrial Electronics Avhandling: Contactless Test of Circuit Boards Opponent: Professor Heli Jantunen, Department of Electrical Engineering, University of Oulu, Oulu, Finland Ordförande: Professor Jerker Delsing, Institutionen för system- och rymdteknik, Luleå Tekniska Universitet Tid: Måndag 10 november 2014, kl. 10.30 Plats: A109, Luleå tekniska universite

Power and Energy Efficiency Evaluation for HW and SW Implementation of nxn Matrix Multiplication on Altera FPGAs

In addition to the performance, low power design became an important issue in the design process of mobile embedded systems. Mobile electronics with rich features most often involve complex computation and intensive processing, which result in short battery lifetime and particularly when low power design is not taken in consideration. In addition to mobile computers, thermal design is also calling for low power techniques to avoid components overheat especially with VLSI technology. Low power design has traced a new era. In this thesis we examined several techniques to achieve low power design for FPGAs, ASICs and Processors where ASICs were more flexible to exploit the HW oriented techniques for low power consumption. We surveyed several power estimation methodologies where all of them were prone to at least one disadvantage. We also compared and analyzed the power and energy consumption in three different designs, which perform matrix multiplication within Altera platform and using state-of-the-art FPGA device. We concluded that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multipliers on FPGAs and configware is an enormous potential to reduce the energy consumption costs

A novel production process for 10 μm microvias

This work investigates the capability of drilling and metallization of microvias of diameter less than 10 µm with aspect ratios of 1-10, using a fully additive process. The microvia has been produced using a sequential build up layer of urethane through which the via has been produced. The urethane layer is applied using spin-coating. Current process setting produces a 15 µm layer thickness. For thicker urethane, multiple layers are applied. Drilling of the via-hole through is made using 266 nm UV laser. The metallisation of the via-hole was made using a process called Covalent Bonded Metallisation (CBM). This process modifies the urethane surface by a grafting process where polymers are covalently bonded to the surface where metallisation is desired. A roughly 5 µm thin film of the used grafting solution is applied to the substrate surface. The grafting process is initiated by laser which draws the patterns where copper is desired. After laser drawing, the substrate is cleaned with deionized water. Next, the substrate is through a commercial chemical-copper process which builds copper only at the laser initiated patterns. Copper thicknesses of 1 µm is easily achievable. To increase the copper thickness, the substrate may be run into thick building chemical-copper process to achieve thicknesses up to 8 µm

Application of Contactless Testing to PCBs with BGAs and Open Sockets

This paper introduces a practical test method that combines statistics with the contactless test approach. Experiments using real conventional PCBAs have shown the effectiveness of the method, where significant z-scores are obtained to discriminate defective interconnects. The studied test cases involve conventional Printed Circuit Board Assemblies (PCBAs) with open sockets and Ball Grid Array (BGA) packages.Validerad; 2015; Nivå 2; 20140914 (abdren

Contactless Testing of Circuit Interconnects

State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 $\mu$m and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.Validerad; 2015; Nivå 2; 20140510 (abdren

Extracting the Magnetic Properties of Blast Furnace Cokes

This work aims to extract the magnetic properties of cokes used in the furnaces of the Swedish mineral company LKAB.Using Nicolson-Ross-Weir (NRW) algorithm and 10 sample loads of cokes, It has been found that cokes cause an attenuation of0.18 to 4 dB/m and exhibit between 2.8 and 3.7 as mean of magnetic permeability and between 0.075 and 0.11 as mean of losstangent within 10 to 350 MHz. With these figures, cokes will absorb 7.5 to 11 % of the reactive magnetic field energy and convertit to eddy currents due its natural electrical conductivity. The measurements are performed at room temperature.636834 (DISIRE

A novel production process for 10 μm microvias

This work investigates the capability of drilling and metallization of microvias of diameter less than 10 µm with aspect ratios of 1-10, using a fully additive process. The microvia has been produced using a sequential build up layer of urethane through which the via has been produced. The urethane layer is applied using spin-coating. Current process setting produces a 15 µm layer thickness. For thicker urethane, multiple layers are applied. Drilling of the via-hole through is made using 266 nm UV laser. The metallisation of the via-hole was made using a process called Covalent Bonded Metallisation (CBM). This process modifies the urethane surface by a grafting process where polymers are covalently bonded to the surface where metallisation is desired. A roughly 5 µm thin film of the used grafting solution is applied to the substrate surface. The grafting process is initiated by laser which draws the patterns where copper is desired. After laser drawing, the substrate is cleaned with deionized water. Next, the substrate is through a commercial chemical-copper process which builds copper only at the laser initiated patterns. Copper thicknesses of 1 µm is easily achievable. To increase the copper thickness, the substrate may be run into thick building chemical-copper process to achieve thicknesses up to 8 µm